![]() ![]() IACA tells me that the "Block throughput" is still 8 operations due to the extra operations to get the addresses onto a single register.C++ compilers these days have code optimization techniques like loop vectorizer which allows the compilers to generate vector instructions for code written in scalar format. Which tells me that the stores can now use port 7 for addresses and the operations were stored. | 0F | | | | | | | | | | jnz 0xffffffffffffff7a Then IACA tells me: Throughput Analysis Reportīlock Throughput: 8.00 Cycles Throughput Bottleneck: Port4 Per the suggestion below, pd's were replaced with ps's and the addresses were consolidated to a single register, the new code looks like: %define ptr I was under the impression that I could get 2x loads at a time with broadwell with simultaneous loads on ports 2&3. | 0F | | | | | | | | | | jnz 0xffffffffffffff78 ! - instruction not supported, was not accounted in Analysis # - ESP Tracking sync uop was - SSE instruction followed an AVX256 instruction, dozens of cycles penalty is expected * - instruction micro-ops not bound to a port N - port number or number of cycles resource conflict caused delay, DV - Divider pipe (on port 0)ĭ - Data fetch pipe (on ports 2 and 3), CP - on a critical pathį - Macro Fusion with the previous instruction occurred I assemble it with YASM and then do a test with the Intel Architecture Code Analyzer (IACA), which tells me: Throughput Analysis Reportīlock Throughput: 8.00 Cycles Throughput Bottleneck: PORT2_AGU, PORT3_AGU, Port4 I'm doing this on an Intel Broadwell chip with AVX2 instructions in a 32byte aligned environment.Ī baseline loop uses 8 YMM registers at a time to load from one location and nontemporally store to another: %define ptr I'm trying to identify a performance baseline for memory-bound vectorized loops. ![]()
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